Dell EMC OpenManage Server Administrator

Capabilities And Cache Information

Use this screen to view a subset of key functions and properties that each processor supports as well as cache information for and each cache present on that processor.

NOTE: This help page may include information about features not supported by the system. Server Administrator only displays the features that are supported on the system.

User Privileges

Table 1. User Privileges
Selection View Manage
Processor UI User, Power User, Administrator Administrator
BIOS Setup UI Administrator Administrator

Capable

If the processor is capable of a particular function or property, this field displays Yes, otherwise No.

Enabled

If a particular function or property of a processor is enabled, this field displays Yes, otherwise No. If a function cannot be enabled or disabled by user, Not Applicable is displayed.

Deprecated

If a particular function or property of a processor is deprecated, this field displays Yes, otherwise column will not be available.

Capabilities Information For Processor On Connector: CPU1

For Intel:
64-bit Support Supports 64-bit.
Hyperthreading (HT) Intel's implementation of the simultaneous multithreading technology.
Virtualization Technology (VT) Intel's virtualization extension to the 64-bit x86 architecture.
Demand Based Switching (DBS) A power-management technology developed by Intel in which the applied voltage and clock speed for a microprocessor are kept to the minimum necessary to allow optimum performance of required operations.
NOTE: Due to the limitations of the VMware ESXi version 3.5 operating system on the 11th generation Poweredge servers, the Demand Based Switching (DBS) field displays incorrect value.
Execute Disable (XD) Allows properly-written applications to mark off memory space as executable, so that code trying to access space above and beyond that will not be executed.
Turbo Mode Displays the processor capability. This is a processor capability that can increase the CPU frequency when the system is operating below the thermal, power or current limits. Configure this processor capability under the BIOS setup page.
For AMD:
64-bit Support Specifies if the installed processor(s) support 64-bit extensions.
AMD-V Specifies if the additional hardware capabilities provided by virtualization technology are available for use.
NOTE: Changing this option results in a system power down of approx. 3-5 seconds after exiting the system setup program.
PowerNow Allows operating system to dynamically adjust processor power states, voltage, and clocking frequencies depending on workload.
No Execute Specifies whether execute disable memory protection technology is enabled or disabled.

Cache Information For Processor On Connector: CPU 1

Use this window to view cache information for each cache present on the microprocessor.

Cache

Cache is small high-speed memory that contains the most recently accessed pieces of main memory. The cache keeps a copy of data or instructions from main memory for quicker retrieval. Cache decreases the amount of time it takes to move data from main memory to the processor and back again. The processor cache is faster than the system's main RAM.

Cache Information For A Particular Processor On Connector n

Some cache devices are internal to the processors on which they reside. When the cache is internal to a processor, the following fields and their values do not appear in the Cache Information for Processor on Connector n window:

  • Speed
  • Cache Device Supported Type
  • Cache Device Current Type
  • External Socket Name

The following fields are defined for a cache device on a particular processor. Some fields do not appear if the cache is internal to the processor.

NOTE: This help page may include information about cache features that are not supported by the system. Server Administrator only displays the cache features that are supported on the system.
Status Indicates whether the cache on the processor is enabled or disabled.
Level Displays the cache level. Primary level cache (L1) is a very fast memory bank located near the processor execution units. Secondary level cache (L2) is a larger staging area that feeds the primary cache. Tertiary level cache (L3), if available, is an additional, larger memory bank which feeds data to the secondary cache. All of these cache levels are located in the processor.
Max Size Displays the maximum memory that the cache can occupy in KB.
Installed Size Displays the actual size of the cache.
Type Indicates whether the cache type is Data or Unified.
Location Indicates whether the cache is located on the processor or on a chip set outside the processor.
Write Policy Describes how the cache deals with a write cycle.
  • In a Write-Back policy, the cache acts like a buffer. When the processor starts a write cycle, the cache receives the data and stops the cycle. The cache then writes the data back to main memory when the system bus is available.
  • In a Write-Through policy, the processor writes through the cache to main memory. The write cycle does not complete until the data is stored into main memory.
  • If the write policy specifies Varies with Address, then the policy is either write-back or write-through, according to the memory address.
Associativity
  • Fully Associative cache allows any line in main memory to be stored at any location in the cache.
  • 64-Way Set-Associative cache directly maps sixty four specific lines of memory to the same sixty four lines of cache.
  • 48-Way Set-Associative cache directly maps forty eight specific lines of memory to the same forty eight lines of cache.
  • 32-Way Set-Associative cache directly maps thirty two specific lines of memory to the same thirty two lines of cache.
  • 24-Way Set-Associative cache directly maps twenty four specific lines of memory to the same twenty four lines of cache.
  • 20-Way Set-Associative cache directly maps twenty specific lines of memory to the same twenty lines of cache.
  • 16-Way Set-Associative cache directly maps sixteen specific lines of memory to the same sixteen lines of cache.
  • 12-Way Set-Associative cache directly maps twelve specific lines of memory to the same twelve lines of cache.
  • 8-Way Set-Associative cache directly maps eight specific lines of memory to the same eight lines of cache.
  • 4-Way Set-Associative cache directly maps four specific lines of memory to the same four lines of cache.
  • 3-Way Set-Associative cache directly maps three specific lines of memory to the same three lines of cache.
  • 2-Way Set-Associative cache directly maps two specific lines of memory to the same two lines of cache.
  • 1-Way Set-Associative cache directly maps a specific line of memory in the same line of cache.
For example, Line 0 of any page in memory must be stored in Line 0 of cache memory.
Error Correction Type Identifies the type of error checking and correction (ECC) that this memory can perform. For example, single-bit ECC or multibit ECC.
For an explanation of other buttons present on Server Administrator Action pages, see Server Administrator Window Buttons.